More memories and larger memories are being used within integrated circuits (ICs), for example as embedded memory, in various applications. Additionally, as feature sizes become smaller, the percentage of area in the IC devoted to memories has been increasing. Consequently, the total power and the percentage of IC power being consumed by memories, relative to other circuit blocks in the IC, are increasing.
The memory within ICs may comprise one memory instance, which may include a small or a very large number of memory cells. Typically, a large memory instance within an IC may comprise up to a few hundred million memory cells, that is, a few hundred megabits of memory. A relatively small memory instance may comprise, for example, less than one million memory cells, that is, less than one megabit of memory. Alternately, an IC may comprise a plurality of memory instances, each memory instance including a small or a very large number of memory cells. The plurality of memory instances need not have the same number of memory cells relative to one another.
Large memories tend to consume significant power in an IC. Therefore, in order to conserve power, it is known to use multiple memories as building blocks for larger memory, and only power up the block that is currently being used. A disadvantage of this approach, however, is that multiple memories will consume more area due, at least in part, to the added peripheral circuitry required for each memory. Additionally, peripheral circuitry typically consumes more leakage current, which is undesirable.
Accordingly, there exists a need for an improved memory architecture which does not suffer from one or more of the above-described problems associated with conventional memory architectures.